Expertise DescriptionI have more than 40 years experience in the fields of Computer System Design and Computer Architecture with expertise in tool development for power optimization. I have experience with VLSI circuits and systems, system clocking and clocked storage elements, and logic design and machine organization. I have additional experience with low-power design and technology, computer arithmetic: VLSI adders, multipliers, and crypto processors, as well as microprocessor design, and design for testability and fault-tolerant computer design. I have over 15 years expert witness experience with consultation, deposition, and court testimony.
Areas of Expertise
My expert witness experience includes preparing expert witness reports, assisting in claim construction, giving expert opinions on patent and claim construction, studying patents and publications for patent infringement disputes related to computer circuits and logic, as well as giving deposition and courtroom testimony in regards to patent infringement.
My consulting experience includes providing lectures in the area of media processor architecture, clocking and clocked storage elements, power optimization of digital circuits; developing energy-delay optimization methodology and tools; was architect and project leader for a new generation of media processors; performed evaluation of clocked storage elements to be used in SH-5 processor; worked in the development of new type of low-power circuits and logic based on energy-recovery principles; and, worked on the development of high-performance super-scalar BiCMOS processor implementation and design.
My professional experience includes Senior Director of Processor Development, Founder and President for a company working in power optimization, President and CEO for a processor design services firm, Director of Research, Professor Emeritus, Visiting Professor, Computer Engineering Chair and Chair Professor, Architecture/Circuit Design Manager, Research Staff, Engineering Staff, and Research Assistant and Engineer.
Processor power management is my area of expertise. I have been working on processors for 30 years and am considered one of the top in the field in the areas of power-performance optimization and power minimization. I have over 15 years of experience working on patents, cases and testifying.
My PhD thesis was on test and VLSI design for testability. After finishing my PhD in 1982 I worked in the area of VLSI (Chip) testing and testability. I published several papers at international conferences. I understand chip manufacturing, working in the chip processing (manufacturing) of top technology corporation, at the time I wrote my thesis. I understand testability and manufacturability issues.
Awards & Affiliation
|Institute of Electrical and Electronics Engineers|
|National Science Fellowship|
Institute of Electrical and Electronics Engineers