Semiconductor Expert 425651 VT


Expertise Description

I have over 30 years experience in semiconductor development. My expertise includes CMOS, Bipolar, BiCMOS, Silicon on Insulator (SOI), LDMOS, Bipolar-CMOS-DMOS (BCD), CMOS Image Processing, and Silicon Germanium (SiGe). I have experience in electrical design, chip design, layout, circuits, devices, computer aided design (CAD), electronic design automation (EDA), as well as device design, circuit design, layout, and CAD. My reliability expertise includes electrostatic discharge (ESD), latchup, reliability mechanisms, leakage mechanisms, radiation, Soft error rate (SER), and hot electron (hot e). I have more than 5 years expert witness experience.

Areas of Expertise


Expert Witness

My expert witness experience includes: Semiconductor structures; Semiconductor circuits; Electrostatic Discharge (ESD) Protection circuits; Silicon on Insulator (SOI) structures.


Consulting Experience

My consulting services include: Prior art review, Invalidity contention review, Claim review, Failure analysis review, and Discovery process.


Professional Experiences




Relevant Experiences

My expertise includes 25 years of semiconductor development at IBM developing technology on DRAM, SRAM, CPUs, and ASICS. My technology expertise includes MOSFET semiconductor development of the FEOL and BEOL from 0.8 um to 90 nm. My expertise includes DRAM cell development and SRAM design. My expertise is in the area of reliability (latchup, SER, hote, and ESD). My development experience also includes SOI and SiGe development. My expertise also includes power transistor, mixed signal, analog, digital, and SOC at Intersil Corporation. I also served as a consultant for TSMC, and Samsung in 45 nm and 14 nm, respectively.

I have 260 US patents and wrote 10 books on ESD, latchup and EOS.

I am an IEEE Fellow for contributions in CMOS, SOI, and SIGE technologies.

I have a background in failure analysis, reverse engineering of products, reliability engineering, product use, electrical overstress, electrostatic discharge, latchup, soft error rate, and reliability mechanisms,

I have experience with development in computer chips from 1 um to 14 nm technology generations in CMOS, BiCMOS, bipolar, SOI, and SiGe technology.


Education

DegreeSubjectInstitution
Ph.D.Electrical EngineeringUniversity of Vermont
M.S.Electrical EngineeringUniversity of Vermont
Electrical EngineerMIT
Master in Electrical EngineeringMIT

Licenses Certifications

ESD Association certified device design

Awards & Affiliation

IEEE Fellow Award
ESD Association Outstanding Contribution Award

Primary Affiliation

Electrostatic Discharge Association (ESDA)


Partial List of Consulting Expert Witness Cases



SELECT EXPERT